1. Field of the Invention
The present invention relates to a signal processing device, particularly to a signal processing device capable of correcting the distortion of the duty cycle in a data signal having different occurrence probabilities of 0 and 1.
2. Description of the Related Art
If an input signal has a distorted duty cycle, or if the duty cycle of a signal is distorted by variation among transistors in a circuit inside an LSI (Large Scale Integration), the bit error rate of the signal is increased.
In view of this, a binarization circuit has been proposed which corrects the distortion of the duty cycle of, for example, an EFM (Eight-to-Fourteen Modulation) signal or an 8B/10B signal coded to have equal occurrence probabilities of 0 and 1 to maintain the DC (Direct Current) balance (see Japanese Unexamined Patent Application Publication No. 06-334496, for example).